Logic designers use hardware description language (HDL) or schematic capture to model a circuit at different level of abstractions. The circuit model is synthesized to construct a gate-level netlist. System designs that include memory-mapped devices require the logic designer to fully specify the addressability and bus connections of the memory-mapped device in the logic design. Great caution is exercised when specifying the addressability and bus connections for memory-mapped devices interacting with multi-byte system buses. Traditional electronic design automation tool flows require the addressability and data connections of a device to a system bus to be explicitly specified. This includes address matching, lane matching, connections to system bus data bits and any other auxiliary logic.
In the case of an 8-bit system bus, where only byte-wide transactions are supported, the specifications of addressability and bus connections is fairly obvious. The lane-matching function is unnecessary because all transactions are byte-wide. All devices connect to the same bits (bits 7:0) of the data bus. Although specifying the addressability and bus connections may be tedious when designing for an 8-bit system bus, there is little danger of accidentally specifying inconsistent addressability and bus connections.
In the case of a 32-bit system bus, where byte-wide, halfword-wide, and word-wide transactions are supported, the connections between the device and the system bus are much more complex. The interdependencies between the address-matching function, the lane-matching function, and the connections to the data bus make it much more likely that the logic designer will accidentally specify inconsistent addressability and bus connection information.
Because the bus connections and lane-matching function must be consistent with the address-matching function, it is not possible to change the address of a memory-mapped device without invalidating the lane-matching function and bus connectivity.